[tech] The Star 910/VP

[David Luyer]

Here's some details I e-mailed myself ages ago, probably mostly from the 
manual but not completely.  I recall discussing these with someone familiar 
with porting *BSD to various SPARCs and they were not surprised (in fact I 
didn't tell them the error just asked if they knew what instruction 0xD801E01C 
was and they said straight off 'are you getting a memory alignment error?').

Anyway I'm killing this out of my old saved mailbox so if anyone else
finds it useful please keep it :)

David.

Star 910/VP

40MHz Cyprus SPARC.  160MFLOPS single prec/80MFLOPS double prec vector
processor, but that bit's ripped out.

CY7C601 Integer unit.
CY7C602 Floating point unit.
(block diagram shows all significant chips and data flows)

VME-bus, B-bus and M-bus, vector processor machine, most scalar stuff
seems to be VME-bus (the other holds only memory and CPU and the now
removed vector processor).

OpenBSD:
Memory alignment error with PC 0x00008578.  Instruction "0xD801E01C".

NetBSD:
Memory alignment error with PC 0x00009450.  Instruction "0xD801E01C".

>From the architecture manual (goes down to the bitlevel and describes
every clock cycle of the bus transactions and every bit of the registers
and timing ok instructions, so possibly quite useful),

M-bus (brief summary of interface specs):

64-bit, fully synchronous, multiplexed bi-directional address and data bus.
all signals are sampled on the rising edge of the system clock.
bus transfer sizes 1, 2, 4, 8, 16, 32, 64, 128 bytes.
read or write transfers clocked every cycle (25ns).

B-bus (brief summary of the general overview bit again):

fully syncronous, non-multiplexed 32-bit address and 64-bit bi-directional data
bus.  all signals are sampled on the clock rising edge.  can operate in a
block or burst mode.  all control signals are asserted one clock cycle before
the assertion of the address bus or data bus or both.  bus transactions can be
initiated on every clock cycle (25ns).

B-bus seems to be used between vector DMA and system memory, which doesn't
matter since the vector processor isn't there.

B-bus transfers around 320Mbytes/sec - for a single bus in 1991, that ain't
bad.  In 1998 it'd still be ok :)  (most internal busses counters etc go
at this 320Mbyte/sec or the slower 160Mbyte/sec in special cases).